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preliminary rev. 0.3 3/07 copyright ? 2007 by silicon laboratories si5367 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5367 p-p rogrammable p recision c lock m ultiplier description the si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. the si5367 accepts four clock inputs ranging from 10 to 707 mhz and generates five frequency-multiplied clock outputs ranging from 10 to 945 mhz and select frequencies to 1.4 ghz. the device provides virtually any frequency translation combination across this operating range. the outputs are divided down separately from a common source. the si5367 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. the si5367 is based on silicon laboratories' 3rd- generation dspll ? technology, which provides any-rate frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. operatin g from a single 1.8 or 2.5 v supply, the si5367 is ideal for providing clock multiplication in high performance timing applications. applications sonet/sdh oc-48/oc-192 line cards gbe/10gbe, 1/2/4/ 8/10gfc line cards itu g.709 and custom fec line cards wireless basestations data converter clocking xdsl sonet/sdh + pdh clock synthesis test and measurement features generates any frequency from 10 to 945 mhz and select frequencies to 1.4 ghz from an input frequency of 10 to 710 mhz low jitter clock outputs w/jitter generation as low as 0.6 ps rms (50 khz?80 mhz) integrated loop filter with selectable loop bandwidth (30 khz to 1.3 mhz) four clock inputs w/manual or automatically controlled hitless switching five clock outputs with selectable signal format (lvpecl, lvds, cml, cmos) support for itu g.709 fec ratios (255/238, 255/237, 255/236) los alarm outputs digitally-controlled output phase adjust i 2 c or spi programmable settings on-chip voltage regulator for 1.8 or 2.5 v 10% operation small size: 14 x 14 mm 100-pin tqfp pb-free, rohs compliant p reliminary d ata s heet i 2 c/spi port clock select ckout2 ckin1 ckout1 ckin2 control nc1 nc2 ckin3 ckin4 ckout4 nc4 ckout5 nc5 vdd (1.8 or 2.5 v) gnd n32 n31 dspll ? n2 ckout3 nc3 n33 n34 device interrupt los alarms
si5367 2 preliminary rev. 0.3 table 1. performance specifications (v dd = 1.8 or 2.5 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.25 2.5 2.75 v 1.62 1.8 1.98 v supply current i dd f out = 622.08 mhz all ckouts enabled lvpecl format output ?394435ma only ckout1 enabled ? 253 284 ma f out = 19.44 mhz all ckouts enabled cmos format output ?278321ma only ckout1 enabled ? 229 261 ma tristate/sleep mode ? tbd tbd ma input clock frequency (ckin1, ckin2, ckin3, ckin4) ck f input frequency and clock multiplication ra tio determined by programming device pll dividers. consult silicon labo- ratories configuration software dspll sim or any-rate preci- sion clock family reference manual at www.silabs.com/tim- ing to determine pll divider settings for a given input fre- quency/clock multiplication ratio combination. 10 ? 707.35 mhz output clock frequency (ckout1, ckout2, ckout3, ckout4, ckout5) ck of 10 970 1213 ? ? ? 945 1134 1417 mhz input clocks (ckin1, ckin2, ckin3, ckin4) differential voltage swing ckn dpp 0.25 ? 1.9 v pp common mode voltage ckn vcm 1.8 v 10% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v rise/fall time ckn trf 20?80% ? ? 11 ns duty cycle ckn dc whichever is less 40 ? 60 % 50 ? ns output clocks (ckout1, ck out2, ckout3, ckout4, ckout5) common mode v ocm lvpecl 100 ? load line-to-line v dd ? 1.42 ?v dd ? 1.25 v differential output swing v od 1.1 ? 1.9 v single ended output swing v se 0.5 ? 0.93 v note: for a more comprehensive listing of de vice specifications, please consult the silicon laborat ories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing .
si5367 preliminary rev. 0.3 3 rise/fall time cko trf 20?80% 230 350 ps duty cycle cko dc 45 ? 55 % pll performance jitter generation j gen f out = 622.08 mhz, lvpecl output format 50 khz?80 mhz ? 0.6 tbd ps rms 12 khz?20 mhz ? 0.6 tbd ps rms 800 hz?80 mhz ? tbd tbd ps rms jitter transfer j pk ?0.050.1db phase noise cko pn f out = 622.08 mhz 100 hz offset ? tbd tbd dbc/hz 1 khz offset ? tbd tbd dbc/hz 10 khz offset ? tbd tbd dbc/hz 100 khz offset ? tbd tbd dbc/hz 1 mhz offset ? tbd tbd dbc/hz subharmonic noise sp subh phase noise @ 100 khz offset ? tbd tbd dbc spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ? tbd tbd dbc package thermal resistance junction to ambient ja still air ? 40 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 2.75 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v operating junction temperature t jct ?55 to 150 oc storage temperature range t stg ?55 to 150 oc esd hbm tolerance (100 pf, 1.5 k ? )2kv esd mm tolerance 200 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications (continued) (v dd = 1.8 or 2.5 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit note: for a more comprehensive listing of de vice specifications, please consult the silicon laborat ories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing .
si5367 4 preliminary rev. 0.3 figure 1. typical phase noise plot 155.52 mhz in, 622.08 mhz out -160 -140 -120 -100 -80 -60 -40 -20 0 100 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz )
si5367 preliminary rev. 0.3 5 figure 2. si5367 typical application circuit (i 2 c control mode) figure 3. si5367 typical application circuit (spi control mode) si5367 ckin1+ ckin1? int_alm cnb rst ckout1+ ckout1? vdd gnd input clock sources* serial data serial clock reset interrupt/alarm output indicator ckinn invalid indicator (n = 1 to 3) clock outputs sda scl i2c interface serial port address a[2:0] cmode control mode (l) ckout5+ ckout5? ckin4+ ckin4? assumes differential lvpecl termination (3.3 v) on clock inputs. *note: ferrite bead system power supply c 10 c 1?9 0.1 f 1 f 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v si5367 ckin1+ ckin1? int_alm cnb spi interface rst ckout1+ ckout1? vdd gnd reset interrupt/alarm output indicator ckin_n invalid indicator (n = 1 to 3) serial data out serial data in sdo sdi serial clock scl slave select ss cmode control mode ckout5+ ckout5? ckin4+ ckin4? input clock sources* 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v clock outputs 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? ferrite bead system power supply c 10 c 1?9 0.1 f 1 f assumes differential lvpecl termination (3.3 v) on clock inputs. *note:
si5367 6 preliminary rev. 0.3 1. functional description the si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. the si5367 accepts four clock inputs ranging from 10 to 707 mhz and generates five frequency-multiplied clock outputs ranging from 10 to 945 mhz and select frequencies to 1.4 ghz. the device provides virtually any frequency translation combination across this operating range. independent dividers are available for every input clock and output clock, so the si5367 can accept input clocks at different frequencies and it can generate outpu t clocks at different frequencies. the si5367 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. silicon laboratories offers a pc- based software utility, dspll sim , that can be used to determine the optimum pll divider settings for a given input frequency/clock multip lication ratio combination that minimizes phase noise and power consumption. this utility can be downloaded from www.silabs.com/timing . the si5367 is based on s ilicon laboratories' 3rd- generation dspll ? technology, which provides any- rate frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5367 pll loop bandwidth is digitally programmable and supports a range from 30 khz to 1.3 mhz. the dspll sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. the si5367 monitors all input clocks for loss-of-signal and provides a los alarm when it detects missing pulses on its inputs. in the case when the input clocks enter alarm conditions, the pll will freeze the dco output frequency near its last value to maintain operation with an internal state close to the last valid operating state. the si5367 has five differential clock outputs. the signal format of the clock outputs is programmable to support lvpecl, lvds, cml, or cmos loads. if not required, unused clock outputs can be powered down to minimize power consumption. the phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. in addition, the phase of each output clock may be adjusted in relation to the other output clocks. the resolution varies from 800 ps to 2.2 ns depending on the pll divider settings. consult the dspll sim configuration software to determine the phase offset resolution for a given input clock/clock multiplication ratio combination. for system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal dspll. the device is powere d by a single 1.8 or 2.5 v supply. 1.1. further documentation consult the silicon laborato ries any-rate precision clock family reference manual (frm) for more detailed information about the si5367. the frm can be downloaded from www.silabs.com/timing . silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. this utility can be downloaded from www.silabs.com/timing .
si5367 preliminary rev. 0.3 7 2. pin descriptions: si5367 table 3. si5367 pin descriptions pin # pin name i/o signal level description 1, 2, 4, 17, 20, 22, 23, 24, 25, 37, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 66, 67, 72, 73, 74, 75, 80, 85, 95 nc no connect. these pins must be left unconnected for normal opera- tion. 3rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal logic to a known state and forces the device registers to their default value. clock outputs are tristated during reset. after rising edge of rst signal, the device will perf orm an intern al self-cali- bration. this pin has a weak pull-up. note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49 nc gnd c2b gnd c1b c3b int_alm gnd nc vdd ckin3+ ckin3? vdd ckin1+ ckin1? ckin2+ ckin2? vdd ckin4+ ckin4? nc sdi nc nc a1 a0 gnd vdd sda_sdo scl c2a c1a cs1_c4a nc nc nc ckout3+ cmode ckout3? nc ckout1+ ckout1? ckout5+ ckout5? vdd ckout2+ ckout2? nc ckout4+ nc ckout4? 17 20 19 18 24 23 22 21 25 74 73 72 71 70 69 68 67 66 65 75 100 89 90 91 92 93 94 95 96 97 98 99 76 77 78 79 80 81 82 83 84 85 86 87 88 rst nc nc vdd gnd cs0_c3a gnd gnd gnd nc nc nc gnd vdd gnd gnd gnd gnd gnd gnd gnd gnd vdd a2_ss gnd nc vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd nc nc nc nc nc vdd nc nc nc nc nc nc nc si5367 gnd pad
si5367 8 preliminary rev. 0.3 5, 6, 15, 27, 32, 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 v dd vdd supply v dd . the device operates from a 1.8 or 2.5 v supply. bypass capacitors should be associated with the following v dd pins: pins bypass cap 5, 6 0.1 f 15 0.1 f 27 0.1 f 62, 63 0.1 f 76, 79 1.0 f 81, 84 0.1 f 86, 89 0.1 f 91, 94 0.1 f 96, 99, 100 0.1 f 7, 8, 14, 16, 18, 19, 21, 26, 28, 31, 33, 36, 38, 41, 43, 46, 64, 65 gnd gnd supply ground. this pin must be connected to system ground. minimize the ground path impedance for optimal performance. 9c1bolvcmos ckin1 invalid indicator. this pin performs the ck1_bad function if ck1_bad_pin = 1 and is tristated if ck1_bad_pin =0. active polarity is controlled by ck_bad_pol . 0 = no alarm on ckin1. 1 = alarm on ckin1. 10 c2b o lvcmos ckin2 invalid indicator. this pin performs the ck2_bad function if ck2_bad_pin = 1 and is tristated if ck2_bad_pin =0. active polarity is controlled by ck_bad_pol . 0 = no alarm on ckin2. 1 = alarm on ckin2. 11 c3b o lvcmos ckin3 invalid indicator. this pin performs the ck3_bad function if ck3_bad_pin = 1 and is tristated if ck3_bad_pin =0. active polarity is controlled by ck_bad_pol . 0 = no alarm on ckin3. 1 = alarm on ckin3. table 3. si5367 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map.
si5367 preliminary rev. 0.3 9 12 int_alm o lvcmos interrupt/alarm output indicator. this pin functions as a maskable interrupt output with active polarity controlled by the int_pol register bit. the int output function can be turned off by setting int_pin = 0. if the alrmout function is desired instead on this pin, set alrmout_pin = 1 and int_pin =0. 0 = alrmout not active. 1 = alrmout active. the active polarity is controlled by ck_bad_pol . if no function is selected, the pin tristates. 13 57 cs0_c3a cs1_c4a i/o lvcmos input clock select/ ckin3 or ckin4 active clock indi- cator. if manual clock selection is chosen, and if cksel_pin = 1, the cksel pins co ntrol clock selection and the cksel_reg bits are ignored. if cksel_pin =0, the cksel_reg register bits control this function and these inputs tristate. if these pins are not functioning as the cs [1:0] inputs and auto clock selection is enabled, then they serve as the ckin_n active clock indicator. 0 = ckin3 (ckin4) is not the active input clock 1 = ckin3 (ckin4) is currently the active input to the pll the ckn_actv_reg bit always reflects the active clock status for ckin_n. if ckn_actv_pin = 1, this status will also be reflected on the cna pin with active polarity con- trolled by the ck_actv_pol bit. if ckn_actv_pin = 0, this output tristates. this pin has a weak pull-down. 29 30 ckin4+ ckin4? imulti clock input 4. differential clock input. this input can also be driven with a single-ended signal. ckin4 serves as the frame sync input associated with the ckin2 clock when ck_config_reg =1. 34 35 ckin2+ ckin2? imulti clock input 2. differential input clock. this input can also be driven with a single-ended signal. table 3. si5367 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map. cs[1:0] active input clock 00 ckin1 01 ckin2 10 ckin3 11 ckin4
si5367 10 preliminary rev. 0.3 39 40 ckin3+ ckin3? imulti clock input 3. differential clock input. this input can also be driven with a single-ended signal. ckin3 serves as the frame sync input associated with the ckin1 clock when ck_config_reg =1. 44 45 ckin1+ ckin1? imulti clock input 1. differential clock input. this input can also be driven with a single-ended signal. 58 c1a o lvcmos ckin1 active clock indicator. this pin serves as the ckin1 active clock indicator. the ck1_actv_reg bit always reflects the active clock sta- tus for ckin1. if ck1_actv_pin = 1, this status will also be reflected on the c1a pin with active polarity con- trolled by the ck_actv_pol bit. if ck1_actv_pin = 0, this output tristates. 59 c2a o lvcmos ckin2 active clock indicator. this pin serves as the ckin2 active clock indicator. the ck2_actv_reg bit always reflects the active clock sta- tus for ckin_2. if ck2_actv_pin = 1, this status will also be reflected on the c2a pin with active polarity con- trolled by the ck_actv_pol bit. if ck2_actv_pin = 0, this output tristates. 60 scl i lvcmos serial clock. this pin functions as the serial port clock input for both spi and i 2 c modes. this pin has a weak pull-down. 61 sda_sdo i/o lvcmos serial data. in i 2 c microprocessor control mode (cmode = 0), this pin functions as the bidirectional serial data port.in spi microprocessor control mode (cmode = 1), this pin functions as the serial data output. 68 69 a0 a1 ilvcmos serial port address. in i 2 c control mode (cmode = 0), these pins function as hardware controlled address bits. in spi control mode (cmode = 1), these pins are ignored. this pin has a weak pull-down. 70 a2_ss ilvcmos serial port address/slave select . in i 2 c microprocessor control mode (cmode = 0), this pin functions as a hardware controlled address bit. in spi microprocessor control mode (cmode = 1), this pin functions as the slave select input. this pin has a weak pull-down. table 3. si5367 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map.
si5367 preliminary rev. 0.3 11 71 sdi i lvcmos serial data in. in spi microprocessor control mode (cmode = 1), this pin functions as the serial data input. in i 2 c microprocessor control mode (cmode = 0), this pin is ignored. this pin has a weak pull-down. 77 78 ckout3+ ckout3? omulti clock output 3. differential clock outp ut. output signal format is selected by sfout3_reg register bits. output is differential for lvpecl, lvds, and cml comp atible modes. for cmos format, both output pins drive identical single-ended clock outputs. 82 83 ckout1? ckout1+ omulti clock output 1. differential clock outp ut. output signal format is selected by sfout1_reg register bits. output is differential for lvpecl, lvds, and cml comp atible modes. for cmos format, both output pins drive identical single-ended clock outputs. 87 88 ckout5? ckout5+ omulti clock output 5. differential clock outp ut. output signal format is selected by sfout5_reg register bits. output is differential for lvpecl, lvds, and cml comp atible modes. for cmos format, both output pins drive identical single-ended clock outputs. 90 cmode i 3-level control mode. selects i 2 c or spi control mode for the device. 0=i 2 c control mode. 1 = spi control mode. 92 93 ckout2+ ckout2? omulti clock output 2. differential clock outp ut. output signal format is selected by sfout2_reg register bits. output is differential for lvpecl, lvds, and cml comp atible modes. for cmos format, both output pins drive identical single-ended clock outputs. 97 98 ckout4? ckout4+ omulti clock output 4. differential clock outp ut. output signal format is selected by sfout4_reg register bits. output is differential for lvpecl, lvds, and cml comp atible modes. for cmos format, both output pins drive identical single-ended clock outputs. gnd pad gnd pad gnd supply ground pad. the ground pad must provide a low thermal and electri- cal impedance to a ground plane. table 3. si5367 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map.
si5367 12 preliminary rev. 0.3 3. ordering guide ordering part number output clock frequency range package temperature range SI5367A-B-GQ 10?945 mhz 970?1134 mhz 1.213?1.417 ghz 100-pin 14 x 14 mm tqfp ?40 to 85 c si5367b-b-gq 10?808 mhz 100-pin 14 x 14 mm tqfp ?40 to 85 c si5367c-b-gq 10?346 mhz 100-pin 14 x 14 mm tqfp ?40 to 85 c
si5367 preliminary rev. 0.3 13 4. package outl ine: 100-pin tqfp figure 4 illustrates the package details for the si5367. table 4 lis ts the values for the di mensions shown in the illustration. figure 4. 100-pin thin quad flat package (tqfp) table 4. 100-pin package diagram dimensions dimension min nom max dimension min nom max a ? ? 1.20 e 16.00 bsc. a1 0.05 ? 0.15 e1 14.00 bsc. a2 0.95 1.00 1.05 e2 3.85 4.00 4.15 b 0.17 0.22 0.27 l 0.45 0.60 0.75 c 0.09 ? 0.20 aaa ? ? 0.20 d 16.00 bsc. bbb ? ? 0.20 d1 14.00 bsc. ccc ? ? 0.08 d2 3.85 4.00 4.15 ddd ? ? 0.08 e0.50 bsc. 0o 3.5o 7o notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant aed-hd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components.
si5367 14 preliminary rev. 0.3 5. recommended pcb layout figure 5. pcb land pattern diagram
si5367 preliminary rev. 0.3 15 table 5. pcb land pattern dimensions dimension min max e0.50 bsc. e 15.40 ref. d 15.40 ref. e2 3.90 4.10 d2 3.90 4.10 ge 13.90 ? gd 13.90 ? x ? 0.30 y1.50 ref. ze ? 16.90 zd ? 16.90 r1 0.15 ref r2 ? 1.00 notes (general): 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stencil design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness shou ld be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5367 16 preliminary rev. 0.3 d ocument c hange l ist revision 0.1 to revision 0.2 changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 3. updated ?2. pin descriptions: si5367?. changed fsout (pins 87 and 88) to clkout5. changed fs_align (pin 21) control pin to gnd. changed pin 16 to ground. revision 0.2 to revision 0.3 removed references to latency control, inc, and dec pins. updated block diagram on page 1. added figure 1, ?typical phase noise plot,? on page 4. updated ?2. pin descriptions: si5367?. changed font of register names to underlined italics . updated "3. ordering guide" on page 12. added ?5. recommended pcb layout?.
si5367 preliminary rev. 0.3 17 n otes :
si5367 18 preliminary rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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